A semiconductor memory device typically includes an array of memory cells arranged in rows and columns, with each memory cell configured to store a data bit. The memory cells within a given row of the array are coupled to a common wordline, while the memory cells within a given column of the array are coupled to a common bitline. Thus, the array includes a memory cell at each point where a wordline intersects with a bitline.
In a semiconductor memory device of the type described above, data may be written to or read from the memory cells of the array using a memory cycle that is divided into a precharge phase and an active phase, with the precharge phase being used to precharge the bitlines to a precharge voltage, and the active phase being used to read or write one or more memory cells of the array. Reading a given memory cell generally comprises transferring data stored within that cell to its corresponding bitline, and writing a given memory cell generally comprises transferring data into that cell from its corresponding bitline.
Memory cell access time is becoming an increasingly important issue in memory device design. For example, excessive memory cell access times can lead to performance bottlenecks in high speed processors. Conventional approaches to reading data from a memory cell include the use of differential balanced sense amplifiers or single-ended unbalanced sense amplifiers. In a typical conventional arrangement, a given sense amplifier output node is coupled to a latch. For each read memory cycle, the sense amplifier is turned on in order to sense data on a corresponding bitline, and then turned off once the sensed data at its output node is stored in the latch, responsive to a sense amplifier enable signal.
Operation of the latch generally requires a separate latch control signal. In order to establish proper timing between the sense amplifier enable signal and the separate latch control signal, it is often necessary for inverters or other circuitry to be inserted at the control input of the latch. Also, it can be very difficult to maintain the appropriate timing margins over process, voltage and temperature (PVT) variations. Moreover, transistor mismatch may require that multiple additional inverters be inserted between an internal node of the sense amplifier and its output node. Accordingly, the significant amounts of additional circuitry required for each sense amplifier and its associated latch in order to address the above-noted signal timing and transistor mismatch concerns can unduly increase the required circuit area and power consumption of the memory device, particularly in view of the large number of sense amplifiers usually present in a given such device. In addition, signal delays attributable to the inclusion of additional inverters and other circuitry can lead to longer memory cell access times.